The 68000 Microprocessor

Last update: 11-Apr-00

        Author: I. Scott MacKenzie

        Publisher: Prentice Hall

        Year: 1995

        Edition: First

        ISBN: 0-02-373654-2

        Photo available

        Information on the 68KMB Educational Package

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        Contents of the floppy disk provided with the book ( ZIP file - 425k)

        Lab manual for the course ( pdf format - 400k)

        Transparency masters ( pdf format - 650k)

        Solutions to even-numbered questions (available to instructors only, contact Prentice-Hall)

Short Table of Contents

Chapter 0 Foundations
Chapter 1 Microcomputer Concepts
Chapter 2 The 68000 Microprocessor
Chapter 3 Instruction Set
Chapter 4 Assembly Language Programming
Chapter 5 Programming Examples
Chapter 6 Exception Processing
Chapter 7 Input/Output
Chapter 8 The 68KMB
Chapter 9 Interface Examples
Chapter 10 Beyond the 68000
Appendix A Condition Codes Computation
Appendix B Instruction Definitions
Appendix C Machine Language Summary
Appendix D Instruction Execution Times
Appendix E MON68K
Appendix F PAL Replacement Circuit
Appendix G 68000 Data Sheet
Appendix H 68681 Data Sheet
Appendix I 6821 Data Sheet
Solutions to Odd-Numbered Problems
Bibliography

Detailed Table of Contents

Chapter 0 - Foundations

0.1. Introduction
0.2. Representation of Information
0.2.1. Number Systems
0.2.2. Conversion Between Bases
0.2.3. Bytes and Kilobytes
0.2.4. 1s and 2s Complements
0.2.5. Signed Numbers
0.2.6. Real Numbers
0.2.7. Floating-Point Numbers
0.2.8. Binary-Coded Decimal
0.2.9. ASCII
0.3. Binary Arithmetic
0.3.1. Addition
0.3.2. Simple Subtraction
0.3.3. Addition and Subtraction Using 2s Complement
0.3.4. Multiplication
0.3.5. Division
0.4. Logic Gates and Boolean Algebra
0.4.1. The Switch as a Logical Operator
0.4.2. Basic Gates
0.4.3. Extension to Three or More Inputs
0.4.4. EXOR and EXNOR Gates
0.4.5. DeMorgan Transformations
0.4.6. Universality of NAND and NOR Gates
0.4.7. Boolean Identities
0.4.8. Algebraic Manipulation
0.4.9. Timings
0.4.10. Types of Outputs
0.5. Combinational Logic
0.5.1. Half Adder
0.5.2. Full Adder
0.5.3. 4-bit Adder
0.5.4. 4-bit Adder/Subtracter
0.5.5. Decoders
0.6. Sequential Logic
0.6.1. Flip Flops
0.6.2. Registers
0.7. Semiconductor Memory Devices
0.7.1. RAM
0.7.2. ROM
0.8. Problems

Chapter 1 - Microcomputer Concepts

1.1. Introduction
1.2. Block Diagram of a Microcomputer
1.2.1. The Central Processing Unit (CPU)
1.2.2. Semiconductor Memory: RAM and ROM
1.2.3. The Buses: Address, Data, and Control
1.2.4. Peripheral Devices
1.3. Memory Organization and Hierarchy
1.4. The Memory Map
1.4.1. Dividing the Memory Space
1.5. The Development Environment
1.5.1. The Development Cycle
1.5.2. Software Development
1.5.3. Hardware Development
1.5.4. Integration and Verification
1.5.5. Commands and Environments
1.6. Summary
1.7. Problems

Chapter 2 - The 68000 Microprocessor

2.1. Introduction
2.2. Programmer's Mode
2.2.1. Data Register
2.2.2. Address Register
2.2.3. Program Counte
2.2.4. Stack Pointe
2.2.5. Status Register
2.3. Memory Organization
2.4. Addressing Modes
2.4.1. Data Register Direct
2.4.2. Address Register Direct
2.4.3. Absolute Short
2.4.4. Absolute Long
2.4.5. Register Indirect
2.4.6. Postincrement Register Indirect
2.4.7. Predecrement Register Indirect
2.4.8. Register Indirect With Offset
2.4.9. Register Indirect With Index and Offset
2.4.10. PC-Relative With Offset
2.4.11. PC-Relative With Index and Offset
2.4.12. Immediate
2.4.13. Implied Register
2.4.14. Relative Addressing
2.4.15. Addressing Mode Categories
2.5. Hardware Summary
2.5.1. Address Bus
2.5.2. Data Bus
2.5.3. Address Strobe
2.5.4. Read/Write
2.5.5. Upper and Lower Data Strobes
2.5.6. Data Transfer Acknowledge
2.5.7. Bus Request
2.5.8. Bus Grant
2.5.9. Bus Grant Acknowledge
2.5.10. Interrupt Priority Level
2.5.11. Bus Error
2.5.12. Reset
2.5.13. Halt
2.5.14. Enable
2.5.15. Valid Peripheral Address
2.5.16. Valid Memory Address
2.5.17. Processor Function Codes
2.5.18. Clock
2.5.19. Power and Ground
2.5.20. Signal Summary
2.6. Data Transfer Timings
2.6.1. Read Cycle
2.6.2. Write Cycle
2.7. Summary
2.8. Problems

Chapter 3 - Instruction Set

3.1 Introduction
3.2 Instruction Categories
3.2.1 Data Movement Instruction
3.2.2 Integer Arithmetic Instruction
3.2.3 Boolean Instructions
3.2.4 Shift and Rotate Instructions
3.2.5 Bit Manipulation Instructions
3.2.6 Binary-Coded Decimal Instructions
3.2.7 Program Flow Instructions
3.2.8 System Control Instructions
3.3 Machine Language Format
3.3.1 Hand Assembly
3.3.2 Disassembly
3.4 Instruction Timings
3.5 Summary
3.6 Problems

Chapter 4 - Assembly Language Programming

4.1. Introduction
4.2. Assembler Operation
4.2.1. Assembler Invocation
4.2.2. Pass One
4.2.3. Pass Two
4.3. Assembly Language Program Format
4.3.1. Label Field
4.3.2. Mnemonic Field
4.3.3. Operand Field
4.3.4. Comment Field
4.4. Special Assembler Symbols
4.4.1. The Location Counter
4.4.2. Indirect Address
4.4.3. Immediate Data Constants
4.4.4. Data Address
4.4.5. Code Address
4.5. Assemble-Time Expressions
4.6. Assembler Directives
4.6.1. ORG
4.6.2. EQU
4.6.3. END
4.6.4. DC
4.6.5. DS
4.6.6. RSEG
4.6.7. EXTERN and PUBLIC
4.7. Modular Programming
4.7.1. Inter-Module Communication
4.7.2. Segments
4.7.3. Relocation
4.7.4. Linker Invocation
4.7.5. Annotated Example
4.8. Programming Style
4.8.1. Labels
4.8.2. Comments
4.8.3. Comment Blocks
4.8.4. Saving Registers on the Stack
4.8.5. Equates
4.8.6. Subroutines
4.8.7. Program Organization
4.9. Summary
4.10. Problems

Chapter 5 - Programming Examples

5.1. Introduction
5.2. Example Programs
5.3. Summary
5.4. Problems

Chapter 6 - Exception Processing

6.1. Introduction
6.2. Privilege States
6.3. Exceptions
6.3.1. Exception Vectors
6.3.2. Multiple Exceptions
6.3.3. Processing of Specific Exceptions
6.4. Reset
6.4.1. Power-on Reset
6.4.2. External Reset
6.4.3. RESET Instruction
6.4.4. Reset Circuitry
6.5. Conclusions
6.6. Problems

Chapter 7 - Input/Output

7.1. Introduction
7.2. Unconditional I/O
7.2.1. Interface to Switches as Input
7.2.2. Interface to LEDs as Output
7.3. Full Decoding vs. Partial Decoding
7.4. Program-conditional I/O
7.5. Memory-mapped I/O vs. I/O-mapped I/O
7.6. Peripheral Interface ICs
7.7. Interrupt-Initiated I/O
7.7.1. Implementation on the 68000
7.7.2. Interrupt Vectoring
7.7.3. Interface Hardware for Interrupts
7.7.4. Interrupt Acknowledge Cycle
7.7.5. Let the ISRs Do the Work
7.7.6. Parameter Passing and Use of the Stack
7.8. Direct Memory Access
7.8.1. Why DMA is Needed
7.8.2. DMA Bus Interface
7.8.3. DMA on the 68000
7.9. Summary
7.10. Problems

Chapter 8 - The 68KMB

8.1. Introduction
8.2. System Summary
8.3. CPU Signals
8.4. System Clock
8.5. Reset Circuit
8.6. Interrupt Circuit
8.7. Address Decoding
8.8. Monitor EPROMs
8.9. User EPROMs
8.10. System/User RAM
8.11. DUART
8.12. Expansion to 6800 Peripherals
8.13. Expansion for RAM, EPROM, and I/O
8.14. DC Power
8.15. Summary
8.16. Problems

Chapter 9 - Interface Examples

9.1. Introduction
9.2. The 68681 DUART
9.3. RS232C Serial Interface
9.4. Switches and LEDs
9.5. 68681 Timer
9.6. 68681 Timer With Interrupts
9.7. 7-Segment LED Interface
9.8. 4-Digit 7-Segment Display
9.9. 8-Digit 7-Segment Display
9.10. 68681 Input Expansion
9.11 6821 Peripheral Interface Adapter
9.12 Hexadecimal Keypad Interface
9.13 Analog Output
9.14 Digital Sine Wave Generator
9.15 Music Output from a Digital-to-Analog Converter
9.16 Analog Input
9.17 Digitized Speech Input and Playback
9.17A Conclusions
9.18 Design Notes
9.19 Problems

Chapter 10 - Beyond the 68000

10.1. Introduction
10.2. Processors
10.2.1. 68008
10.2.2 68010
10.2.3. 68020
10.2.4. 68030
10.2.5. 68040
10.2.6. 68302, 68340, and 68306
10.3. Coprocessors
10.3.1. 68881
10.3.2. 68882
10.4. Peripheral/Memory Interface ICs
10.5. What's Ahead?

Appendices

A Condition Codes Computation
B Instruction Definitions
C Machine Language Summary
D Instruction Execution Times
E MON68K
F PAL Replacement Circuit
G 68000 Data Sheet
H 68681 Data Sheet
I 6821 Data Sheet
Solution to Odd-Numbered Problems
Bibliography